I. Field of the Invention
The present invention relates to a semiconductor device with an interconnection layer for interconnecting semiconductor regions of different conductivity types and a method of manufacturing the same.
II. Description of the Prior Art
Semiconductor integrated circuits, especially, semiconductor memory devices such as RAMs (Random Access Memories) and ROMs (Read Only Memories) have become increasingly miniaturized in recent years.
FIG. 1 is a circuit diagram showing the configuration of a memory cell in a conventional complementary metal-oxide-semiconductor (CMOS) static RAM memory as one of the above-mentioned RAMs. The memory cell has data storage flip-flop circuit 17 and transfer gate n-channel metal-oxide-semiconductor (MOS) transistors 23 and 24. In circuit 17, input terminals of CMOS inverter 15, consisting of p-channel MOS transistor 11 and n-channel MOS transistor 13, and CMOS inverter 16, consisting of p-channel MOS transistor 12 and n-channel MOS transistor 14, are connected to each other's respective output terminals. The source-drain path of transistor 23 is inserted between data storage node 18 of circuit 17 and bit line 20. The gate of transistor 23 is connected to word line 22. The source-drain path of transistor 24 is inserted between data storage node 19 of circuit 17 and bit line 21. The gate of transistor 24 is connected to word line 22. Transistors 11 to 14, 23, and 24 are of enhancement type.
FIG. 2 is a circuit diagram showing the configuration of an E/R type static RAM memory cell consisting of high impedance resistors and enhancement type MOS transistors. In this memory cell, high impedance load resistors 25 and 26 are used in place of transistors 11 and 12 of circuit 17 in CMOS static RAM memory cell in FIG. 1.
A comparison of the characteristics of the memory cells in FIGS. 1 and 2 is as follows. In consideration of power consumption in the standby mode and data storage holding capacity, the CMOS static RAM cell is superior to the E/R type static RAM cell. For example, power consumption of the CMOS static RAM cell is determined only by the leakage current of the respective transistors. The leakage current of transistors 13 and 14 as operating transistors in the E/R type static RAM cell must be supplied by resistors 25 and 26 as high impedance elements. In order to statically hold the data, a current which is about 100 times the leakage current of transistors 13 and 14 must be supplied to node 18 or 19. Since resistors 25 and 26 are normally made of polycrystalline silicon, it is difficult to maintain a low current level of resistors 25 and 26 when element micropatterning advances.
Operational stability (i.e., a power source margin, a noise margin, and resistance to soft error caused by alpha-rays) of the CMOS static RAM cell is superior to the E/R type static RAM cell. This is because the load elements are transistors (active elements) 11 and 12, and data storage nodes 18 and 19 can easily restore a high voltage level.
The size of the CMOS static RAM cell is larger than that of the E/R type static RAM cell. Since the cell size determines the chip size, a small cell size provides advantages in integration and manufacturing cost. When a normal transfer gate is used in the E/R type static RAM cell, the cell consists of four MOS transistors and two resistors, as shown in FIG. 2. The resistors can be easily formed above the active elements (to be described later). For this reason, the cell size can be decreased, and thus the packing density can be increased.
The CMOS static RAM cell shown in FIG. 3 consists of six MOS transistors and an isolating region required to isolate a p-type element from an n-type element. The size of the CMOS static RAM cell is larger than the E/R type static RAM cell.
FIG. 3 is a plan view of the CMOS static RAM cell. Referring to FIG. 3, reference numeral 31 denotes n-type diffusion regions constituting source and drain regions of n-channel transistors 13 and 14 (FIG. 1); and reference numeral 32 denotes p-type diffusion regions constituting source and drain regions of p-channel transistors 11 and 12 (FIG. 1). Reference numeral 33 denotes a first polycrystalline silicon layer serving as word line 22 of FIG. 1. Transfer gate transistors 23 and 24 are formed at intersection portions 34 and 35 between layer 33 and regions 31.
Reference numerals 36 and 37 denote first polycrystalline silicon layers. Transistor 13, as part of CMOS inverter 15, is formed at intersection portion 38 between layer 36 and region 31, and transistor 14, as part of CMOS inverter 16, is formed at intersection portion 39 between layer 37 and region 31. Furthermore, transistor 11, as part of inverter 15, is formed at intersection portion 40 between layer 36 and region 32, and transistor 12, as part of inverter 16, is formed at intersection portion 41 between layer 37 and region 32.
A right descending hatched line portion in FIG. 3 is second n-type polycrystalline silicon layer 42 connected to ground potential Vss and is connected to region 31 through contact hole 43. Left descending hatched line portions are aluminum wiring region 44 to 47. Layer 44 is one bit line which is connected to region 31 through contact hole 48. Layer 45 is the other bit line connected to region 31 through contact hole 49. Layer 46 is used as an interconnection layer for connecting regions 31 and 32 through contact holes 50 and 51, and to layer 37 as a gate wiring of p-channel MOS transistor 12 through contact hole 52. Layer 47 is used as an interconnection layer for connecting regions 31 and 32 through contact holes 53 and 54 and to layer 36 as the gate wiring of p-channel MOS transistor 11 through contact hole 54.
FIG. 4 is a plan view showing a pattern of an E/R type static RAM cell. Reference numeral 61 denotes n-type diffusion regions serving as source and drain regions of n-channel MOS transistors 13, 14, 23, and 24 (FIG. 2). Reference numeral 62 denotes a first polycrystalline silicon layer serving as word line 22 of FIG. 2. Transfer gate transistors 23 and 24 (FIG. 2) are respectively formed at intersection portions 63 and 64 between layer 62 and region 61.
Reference numerals 65 and 66 also denote first polycrystalline silicon layers. Drive transistors 13 and 14 in FIG. 2 are respectively formed at intersection portions 67 and 68 between layers 65 and 66 and region 61.
A right descending hatched line portion in FIG. 4 is second polycrystalline silicon layer 69 connected to power source voltage Vcc, and part thereof constitutes resistors 25 and 26 in FIG. 2. Left descending hatched line portions are aluminum wiring layers 70, 71, and 72. Layers 71 and 72 constitute a pair of bit lines, as in FIG. 2. Layer 70 is connected to ground potential Vss and to region 61 through contact hole 73.
A cell size of the static RAM cells will be described when the cells are integrated. In the CMOS static RAM cell of FIG. 3, a power source Vss line is second polycrystalline silicon layer 42. A wiring density of aluminum wiring layers 44 to 47 is four per cell. A second polycrystalline silicon layer density is one per cell. On the other hand, in the E/R type static RAM, the two bit lines are aluminum wiring layers, and the high impedance resistor layers are by the second polycrystalline silicon layer regions which are formed above the active elements.
When the area of the CMOS static RAM cell in FIG. 3 is compared with that of the E/R static RAM cell in FIG. 4, its cell area is about 141% that of the cell in FIG. 4. The reason for the increase in cell size in FIG. 3 is the use of aluminum wiring layers. As is apparent from FIGS. 3 and 4, four aluminum wiring layers are used in the cell in FIG. 3, while three aluminum wiring layers are used in the cell in FIG. 4. The width of the CMOS static RAM cell is determined by the number of aluminum wiring layers in the cell. Thus, it is very effective and desirable to decrease the number of aluminum wiring layers for reduction in cell size.
In the E/R type static RAM cell, on the other hand, it is very important to obtain a predetermined length to polycrystalline silicon layers. In the E/R type static RAM cell specifically, a decrease in the cell size in the longitudinal direction, that is, the direction of the length of the aluminum wiring layers is limited.
As described above, the CMOS static RAM cell is superior to the E/R type static RAM cell when various characteristics are taken into consideration, but the CMOS static RAM has limitations in cell size reduction. The E/R type static RAM cell generally has poorer electrical characteristics and limitations in cell size reduction.